The invention pertains to a solid-state image sensing device including a fixed-pattern noise reducing circuit.
FIG. 1 is a diagram illustrating a prior art image sensing device of the same general type to which the invention pertains. The device includes a sensor array chip 15 upon which are fabricated a pixel (picture element) array 12, vertical and horizontal shift registers 11 and 13, and output switches comprising FETs 19. The pixel array 12 includes vertical lines 18 and horizontal lines 20 arranged perpendicular to one another. (Although the vertical lines 18 extend in the horizontal direction in the figure and the horizontal lines 20 in the vertical direction, nevertheless, they are properly termed vertical and horizontal lines, respectively, since the vertical lines 18 are scanned in the vertical direction and the horizontal lines 20 scanned in the horizontal direction.) Light-sensing pixels 14 are formed at each intersection between a vertical line 18 and horizontal line 20. Each pixel schematically is composed of an FET switch 17 and a photosensitive diode 16.
The horizontal lines 20 are connected to the sources of respective output switch FETs 19, the drains of which are connected in common to a line 37. The gates of the FETs are connected to respective outputs of the horizontal shift register 13. The line 37 is connected to a video output terminal pad 23. The terminal pad 23 is coupled externally of the chip 15 to the inverting input of an operational amplifier 41, the noninverting input of which is connected to a source of a reference potential V.sub.REF. Alternatively, the video output can be summed with a reference potential and the sum applied to the inverting input of the amplifier 41. A feedback resistor 42 is connected between the output of the amplifier 41 and the inverting input. The output of the amplifier 41 is also applied to a fixed-pattern noise integrator circuit 43.
In operation, the vertical shift register is operated by clocking signals .phi..sub.V1 and .phi..sub.V2 to activate the lines 18 in sequence. Activation of each of the lines 18 in this manner causes the FETs 17 having gates connected to that line to turn on, thereby transferring signal charges, the magnitudes of which are indicative of the sensed light intensity, from the respective photosensitive diodes 16 to the horizontal lines 20. After the signal charges have been transferred, the horizontal shift register 13 is operated by clocking signals .phi..sub.H1 and .phi..sub.H2 to turn on the FETs 19 in sequence, thereby to transfer the signal charges from the horizontal lines 20 one at a time to the line 37, and thence via the terminal pad 23 to the inverting input of the amplifier 41.
Referring now to the waveform diagrams of FIGS. 2A through 2F, the operation of the abovedescribed device will be further explained. FIGS. 2A and 2B show two pulses from adjacent outputs of the horizontal shift register 13. In response to the pulses of FIGS. 2A and 2B, signal charges, as illustrated by the current signals shown in FIGS. 2C and 2D, from corresponding horizontal lines 20 are transferred via respective FETs 19 to the output line 37. However, the pulses of FIGS. 2C and 2D do not appear in this form on the output line 37. Instead, due to the presence of stray capacitances 31 through 36, the current signal on the output line 37 actually appears as shown in FIG. 2E because of switching transients and induced noise. In fact, as can readily be appreciated from comparing FIGS. 2C and 2D with FIG. 2E, the switching transients and noise components are much greater in magnitude than the actual signal components. The actual signal components show up in the waveform of FIGS. 2E as only a slight drooping in the waveform, as indicated by the difference between the dashed line and adjacent solid-line portions of the indicated waveform. The peak amplitudes of the waveform of FIG. 2E carry little information regarding the signal amplitude. Moreover, the peaks of the waveform FIG. 2E vary from pulse to pulse, thereby resulting in what is known as fixed-pattern noise. The subject of fixed-pattern noise is discussed in more detail in the articles: Nabeyama et al., "All Solid-State Color Camera with Single Chip MOS Imager", IEEE Transactions on Consumer Electronics, Vol. CE-27, February 1981; Imada et al., "Noise of an MOS-type Area Imager", 1982 Conference on Custom Integrated Circuits, Rochester, N.Y.; Aoki et al., "2/3 Inch Format MOS Single Chip Color Imager", IEEE Transactions on Electron Devices, Vol. 29, No. 4, April 1982; and Hodges et al., "Potential of MOS Technologies for Analog Integrated Circuits", IEEE Journal of Solid State Circuits, Vol. SC-13, June 1971, pp. 285-294.
To extract the signal component from the signal of FIG. 2E and to eliminate the fixed-pattern noise, the signal from the output terminal pad 23 is buffered and amplified by the amplifier 41, which converts the current signal to a voltage signal, and then integrated by the fixed-pattern noise integrator 43. As indicated in FIG. 2F, the integrator 43 integrates the amplified signal starting from a time t.sub.0 at the rising edge of a pulse from the horizontal shift register 13 and stops the integration at a time t.sub.1 after all switching transients have died out. Between the time t.sub.1 and a subsequent time t.sub.2, the output from the integrator 43 is read by a subsequent processing circuit (not shown), after which the integrator 43 is reset (with a signal RESET) between times t.sub.2 and t.sub.3 to prepare for the next pulse.
The arrangement of FIG. 1 suffers from the following difficulties: First, the amplifier 41 must have a gain-bandwidth product (GBW) of about 400 to 600 MHz for ordinary video rates to avoid signal distortion which would prevent accurate signal integration. Also, the feedback resistor 42 must have a resistance value in excess of 100 k.OMEGA. to produce a usable signal strength. This high resistance value makes the resistor 42 prone to parasitic effects at high frequencies. Still further, the magnitude of the stray capacitance 36 is many times larger than the internal chip capacitance, thereby increasing the random noise. Finally, the large gain-bandwidth product of the amplifier 41 makes the construction of this amplifier unavoidably complex, making it large in size, and further increasing the magnitude of the stray capacitance 36.
To reduce the magnitude of the stray capacitance 36, it is possible to move the amplifier 41, feedback resistor 42 and fixed-pattern noise integrator 43 onto the sensor array chip 15. However, doing so is accompanied by other problems. Specifically, the gain-bandwidth product which can be achieved using current MOS integrated circuit techniques is only about 10 to 20 MHz. Also, it is difficult to fabricate the high resistance value feedback resistor and to make the resistance value sufficiently accurate.
Accordingly, it is an object of the present invention to provide an image sensing device which avoids the specific drawbacks of the prior art approaches mentioned above.